/*
 * memsetup-sa1110.S: memory setup for various SA1110 architectures
 *
 * $Id: memsetup-sa1110.S,v 1.8 2001/12/27 18:27:37 erikm Exp $
 *
 * Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 */
/*
 * Documentation:
 * Intel Corporation, "Intel StrongARM SA-1110 Microprocessor
 *     Advanced Developer's manual, December 1999
 *
 * Intel has a very hard to find SDRAM configurator on their web site:
 *   http://appzone.intel.com/hcd/sa1110/memory/index.asp
 *
 * NOTE: This code assumes that an SA1110 CPU *always* uses SDRAM. This
 * appears to be true, but it might be possible that somebody designs a
 * board with mixed EDODRAM/SDRAM memory (which is a bad idea). -- Erik
 *
 * 04-10-2001:	SELETZ
 * - separated memory config for multiple platform support
 * - perform SA1110 Hardware Reset Procedure
 *
 */

.ident "$Id: memsetup-sa1110.S,v 1.8 2001/12/27 18:27:37 erikm Exp $"

#ifdef HAVE_CONFIG_H
# include <blob/config.h>
#endif

#define BLOB_NEED_MEMCONFIG
#include <blob/memsetup.h>
#include <blob/arch.h>

			
.text
MEM_REG_BASE:	.long	0xa0000000
MEM_START:	.long	MEMORY_START

MEMORY_CONFIG:
	.long	MDCNFG_VALUE		/* 0x0  MDCNFG */
	.long	MDCAS00_VALUE		/* 0x04 MDCAS00 */
	.long	MDCAS01_VALUE		/* 0x08 MDCAS01 */
	.long	MDCAS02_VALUE		/* 0x0c MDCAS02 */
	.long	MSC0_VALUE		/* 0x10 MSC0 */
	.long	MSC1_VALUE		/* 0x14 MSC1 */
	.long	MECR_VALUE		/* 0x18 MECR */
	.long	0xdeadbeef		/* 0x1C MDREFR */
	.long	MDCAS20_VALUE		/* 0x20 MDCAS20 */
	.long	MDCAS21_VALUE		/* 0x24 MDCAS21 */
	.long	MDCAS22_VALUE		/* 0x28 MDCAS22 */
	.long	MSC2_VALUE		/* 0x2C MSC2 */
	.long	SMCNFG_VALUE		/* 0x30 SMCNFG */

.globl memsetup
memsetup:
	mov r5, lr

	/* Set up the SDRAM */
	ldr	r0, MEM_REG_BASE
	adr	r1, MEMORY_CONFIG

	ldr	r2, [r1, #MDCNFG ]
	str	r2, [r0, #MDCNFG ]

	ldr	r2, [r1, #MDCAS00 ]
	str	r2, [r0, #MDCAS00 ]

	ldr	r2, [r1, #MDCAS01 ]
	str	r2, [r0, #MDCAS01 ]

	ldr	r2, [r1, #MDCAS02 ]
	str	r2, [r0, #MDCAS02 ]

	ldr	r2, [r1, #MDCAS20 ]
	str	r2, [r0, #MDCAS20 ]

	ldr	r2, [r1, #MDCAS21 ]
	str	r2, [r0, #MDCAS21 ]

	ldr	r2, [r1, #MDCAS22 ]
	str	r2, [r0, #MDCAS22 ]

	/* clear KxDB2 */
	ldr r2, [ r0, #MDREFR ]
	bic r2, r2, #MDREFR_K0DB2
	bic r2, r2, #MDREFR_K1DB2
	bic r2, r2, #MDREFR_K2DB2
	str r2, [ r0, #MDREFR ]

	/* set TRASR and DRI, KxDB2 */
	ldr r2, [ r0, #MDREFR ]
	orr r2, r2, #MDREFR_TRASR(7)
	orr r2, r2, #MDREFR_DRI(12)
	orr r2, r2, #MDREFR_K0DB2
	orr r2, r2, #MDREFR_K1DB2
	orr r2, r2, #MDREFR_K2DB2
	str r2, [ r0, #MDREFR ]

	/* set KxRUN */
	ldr r2, [ r0, #MDREFR ]
	orr r2, r2, #MDREFR_K0RUN
	orr r2, r2, #MDREFR_K1RUN
	orr r2, r2, #MDREFR_K2RUN
	str r2, [ r0, #MDREFR ]

	/* clear SLFRSH */
	ldr r2, [ r0, #MDREFR ]
	bic r2, r2, #MDREFR_SLFRSH
	str r2, [ r0, #MDREFR ]

	/* toggle E1PIN (set -> clear ) */
	ldr r2, [ r0, #MDREFR ]
	orr r2, r2, #MDREFR_E1PIN
	str r2, [ r0, #MDREFR ]

	/* Issue read requests to disabled bank to start refresh */
	ldr	r1, MEM_START
.rept	8	
	ldr	r0, [r1]
.endr

	ldr	r0, MEM_REG_BASE
	adr r1, MEMORY_CONFIG
	
	/* ENABLE SDRAM BANKS */
	ldr	r2, [r0, #MDCNFG ]
	orr	r2, r2, #0x00000003
	orr	r2, r2, #0x00030000
	str	r2, [r0, #MDCNFG]

	/* OPTIONALLY enable Autopowerup/down */
#if 0
	ldr r2, [ r0, #MDREFR ]
	orr r2, r2, #MDREFR_EAPD
	orr r2, r2, #MDREFR_KAPD
	str r2, [ r0, #MDREFR ]
#endif

	ldr	r2, [r1, #MCS0 ]
	str	r2, [r0, #MCS0 ]

	ldr	r2, [r1, #MCS1 ]
	str	r2, [r0, #MCS1 ]

	ldr	r2, [r1, #MCS2 ]
	str	r2, [r0, #MCS2 ]

	ldr	r2, [r1, #SMCNFG ]
	str	r2, [r0, #SMCNFG ]

	ldr	r2, [r1, #MECR ]
	str	r2, [r0, #MECR ]
	
	mov	pc, r5
